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1. general description the pcf8534a is a peripheral device which interfaces to almost any lcd with low multiplex rates. it generates the drive signals for any static or multiplexed lcd containing up to four backplanes and up to 60 segments. in addition, the pcf8534a can be easily cascaded for larger lcd applications. the pcf8534a is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional i 2 c-bus. communication overheads are minimized using display ram with auto-incremented addressing, hardware subaddressing and display memory switching (static and duplex drive modes). the pcf8534a complies with aec-q100 (automotive). 2. features n single-chip lcd controller and driver n selectable backplane drive con?gurations: static or 2, 3 or 4 backplane multiplexing n 60 segment drives: u 30 8-segment numeric characters u 16 15-segment alphanumeric characters u any graphics of up to 240 elements n cascading supported for larger applications n 60 4-bit display data storage ram n wide lcd supply range: from 2.5 v for low threshold lcds up to 6.5 v for guest-host lcds and high threshold (automobile) twisted nematic lcds n internal lcd bias generation with voltage follower buffers n selectable display bias con?gurations: static, 1 2 or 1 3 n wide logic power supply range: from 1.8 v to 5.5 v n lcd and logic supplies may be separated n low power consumption n 400 khz i 2 c-bus interface n compatible with any microprocessors or microcontrollers n no external components n display memory bank switching in static and duplex drive modes n auto-incremented display data loading n versatile blinking modes n silicon gate cmos process pcf8534a universal lcd driver for low multiplex rates rev. 03 10 november 2008 product data sheet
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 2 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 3. ordering information 4. marking 5. block diagram table 1. ordering information type number package name description delivery form version pcf8534ah/1 lqfp80 plastic low pro?le quad ?at package; 80 leads; body 12 12 1.4 mm tape and reel sot315-1 pcf8534au/da/1 pcf8534au wire bond die; 76 bonding pads; 2.91 2.62 0.38 mm chip in tray pcf8534au table 2. marking codes type number marking code pcf8534ah/1 pcf8534ah pcf8534au/da/1 pc8534a-1 fig 1. block diagram of pcf8534a 001aah614 lcd voltage selector clock select and timing blinker timebase oscillator input filters i 2 c-bus controller power-on reset clk sync osc scl sda backplane outputs display control bp0 bp1 bp2 bp3 display segment outputs display register output bank select and blink control 60 s0 to s59 sa0 v dd a0 a1 a2 pcf8534a lcd bias generator v ss v lcd command decode write data control display ram data pointer and auto increment subaddress counter
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 3 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 6. pinning information 6.1 pinning top view. for mechanical details, see figure 23 . fig 2. pcf8534ah/1 pin con?guration (sot315-1) pcf8534ah s31 s10 s32 s9 s33 s8 s34 s7 s35 s6 s36 s5 s37 s4 s38 s3 s39 s2 s40 s1 s41 s0 s42 v lcd s43 v ss s44 sa0 s45 a2 s46 a1 s47 a0 s48 osc s49 sync s50 v dd s51 s30 s52 s29 s53 s28 s54 s27 s55 s26 s56 s25 s57 s24 s58 s23 s59 s22 bp0 s21 bp1 s20 bp2 s19 bp3 s18 n.c. s17 n.c. s16 n.c. s15 n.c. s14 sda s13 scl s12 clk s11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 001aag092
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 4 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates for mechanical details, see figure 24 . fig 3. pcf8534au/da/1 pin con?guration (bare die) f c1 c2 pcf8534a-1 s30 s31 s32 s33 s34 s35 s36 s37 s38 s39 s40 s41 s42 s43 s44 s45 s46 s47 s48 s49 s50 s51 s52 s53 s54 s55 s56 s57 s58 s59 bp0 bp1 bp2 bp3 sda scl clk v dd sync osc a0 a1 a2 sa0 v ss v lcd s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 001aai648 76 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 75 74 73 72 71 70 69 68 67 66 65 64 1 s29 s28 s27 s26 s25 s24 top view s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 5 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 6.2 pin description [1] the substrate (rear side of the die) is wired to v ss but should not be electrically connected. 7. functional description the pcf8534a is a versatile peripheral device designed to interface any microprocessor or microcontroller to a wide variety of lcds. it can directly drive any static or multiplexed lcd containing up to four backplanes and up to 60 segments. the display con?gurations possible with the pcf8534a depend on the number of active backplane outputs required. display con?guration selection is shown in t ab le 4 . all of the display con?gurations can be implemented in the typical system shown in figure 4 . table 3. pin description symbol pin description sot315 bare die s31 to s59 1 to 29 44 to 72 lcd segment output 31 to 59 bp0 to bp3 30 to 33 73 to 76 lcd backplane output 0 to 3 n.c. 34 to 37 - not connected sda 38 1 i 2 c-bus serial data input and output scl 39 2 i 2 c-bus serial clock input clk 40 3 external clock input and output v dd 41 4 supply voltage sync 42 5 cascade synchronization input and output (active low) osc 43 6 enable input for internal oscillator a0 to a2 44 to 46 7 to 9 subaddress counter input 0 to 2 sa0 47 10 i 2 c-bus slave address input 0 v ss 48 11 [1] ground v lcd 49 12 input of lcd supply voltage s0 to s30 50 to 80 13 to 43 lcd segment output 0 to 30 table 4. selection of display con?gurations backplanes segments 7-segment numeric 14-segment numeric dot matrix digits indicator symbols characters indicator symbols 4 240 30 30 16 16 240 (4 60) 3 180 22 26 12 12 180 (3 60) 2 120 15 15 8 8 120 (2 60) 1 60 7 11 4 4 60 (1 60)
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 6 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates the host microprocessor or microcontroller maintains the 2-line i 2 c-bus communication channel with the pcf8534a. biasing voltages for the multiplexed lcd waveforms are generated internally, removing the need for an external bias generator. the internal oscillator is selected by connecting pin osc to v ss . the only other connections required to complete the system are the power supplies (pins v dd , v ss and v lcd ) and the lcd panel selected for the application. 7.1 power-on reset at power-on the pcf8534a resets to a default starting condition: ? all backplane outputs are set to v lcd ? all segment outputs are set to v lcd ? the selected drive mode is: 1:4 multiplex with 1 3 bias ? blinking is switched off ? input and output bank selectors are reset ? the i 2 c-bus interface is initialized ? the data pointer and the subaddress counter are cleared (set to logic 0) ? the display is disabled do not transfer data on the i 2 c-bus after a power-on for 1 ms to enable the reset action to complete. 7.2 lcd bias generator fractional lcd biasing voltages are obtained from an internal voltage divider comprising three series resistors connected between pins v lcd and v ss . the center resistor is switched out of the circuit to provide the 1 2 bias voltage level for the 1:2 multiplex con?guration. 7.3 lcd voltage selector the lcd voltage selector coordinates the multiplexing of the lcd based on the selected lcd drive con?guration. the operation of the voltage selector is controlled by mode set commands from the command decoder. fig 4. typical system con?guration host micro- processor/ micro- controller r t r 2c b sda scl osc 60 segment drives 4 backplanes lcd panel (up to 240 elements) pcf8534a a0 a1 a2 sa0 v dd v ss v ss v dd v lcd 001aah616
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 7 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates t ab le 5 shows the biasing con?gurations applicable to the preferred operating modes together with the biasing characteristics as functions of v oper and the resulting discrimination ratios (d). a practical value for v oper is determined by equating v off(rms) with a de?ned lcd threshold voltage (v th ), typically when the lcd exhibits approximately 10 % contrast. in the static drive mode a suitable choice is v oper > 3v th . multiplex drive ratios of 1:3 and 1:4 with 1 2 bias are possible but the discrimination and hence the contrast ratios are smaller e.g.: for 1:3 multiplex or for 1:4 multiplex the advantage of these modes is the reduction of the lcd full-scale voltage v oper as follows: ? 1:3 multiplex ( 1 2 bias): ? 1:4 multiplex ( 1 2 bias): these compare with v oper =3v off(rms) when 1 3 bias is used. it should be noted that v oper =v lcd . table 5. preferred lcd drive modes: summary of characteristics lcd drive mode number of lcd bias con?guration backplanes levels static 1 2 static 0 1 1:2 2 3 1 2 0.354 0.791 2.234 1:2 2 4 1 3 0.333 0.745 2.237 1:3 3 4 1 3 0.333 0.638 1.915 1:4 4 4 1 3 0.333 0.577 1.732 3 1.732 = 21 3 --------- - 1.528 = ? ?? v oper 6v off rms () 2.449v off rms () == v oper 43 () 3 -------------------- - 2.309v off rms () == v off rms () v oper ------------------------ v on rms () v oper ---------------------- - d v on rms () v off rms () ------------------------ =
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 8 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 7.4 lcd drive mode waveforms 7.4.1 static drive mode the static lcd drive mode is used when a single backplane is provided in the lcd. backplane and segment drive waveforms for this mode are shown in figure 5 . v state1 (t) = v sn (t) - v bp0 (t). v on(rms) = v lcd . v state2 (t) = v (sn + 1) (t) - v bp0 (t). v off(rms) = 0 v. fig 5. static drive mode waveforms mgl745 v ss v lcd v ss v lcd v ss v lcd v lcd - v lcd - v lcd v lcd state 1 0 v bp0 sn sn+1 state 2 0 v (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 1 (on) state 2 (off) t fr
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 9 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 7.4.2 1:2 multiplex drive mode when two backplanes are provided in the lcd, the 1:2 multiplex mode applies. the pcf8534a allows the use of 1 2 bias or 1 3 bias in this mode as shown in figure 6 and figure 7 . v state1 (t) = v sn (t) - v bp0 (t). v on(rms) = 0.791v lcd . v state2 (t) = v sn (t) - v bp1 (t). v off(rms) = 0.354v lcd . fig 6. waveforms for the 1:2 multiplex drive mode with 1 2 bias mgl746 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 2 state 1 v ss v lcd v lcd / 2 v ss v ss v lcd v lcd v ss v lcd v lcd v lcd 0 v 0 v v lcd / 2 v lcd / 2 v lcd / 2 - v lcd - v lcd - v lcd / 2 - v lcd / 2 s n sn+1 t fr
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 10 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates v state1 (t) = v sn (t) - v bp0 (t). v on(rms) = 0.745v lcd . v state2 (t) = v sn (t) - v bp1 (t). v off(rms) = 0.333v lcd . fig 7. waveforms for the 1:2 multiplex drive mode with 1 3 bias mgl747 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 0 v v lcd 2v lcd / 3 - 2v lcd / 3 v lcd / 3 - v lcd / 3 - v lcd - v lcd 0 v v lcd 2v lcd / 3 - 2v lcd / 3 v lcd / 3 - v lcd / 3 s n s n+1 t fr v ss v lcd 2v lcd / 3 v lcd / 3
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 11 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 7.4.3 1:3 multiplex drive mode when three backplanes are provided in the lcd, the 1:3 multiplex drive mode applies, as shown in figure 8 . v state1 (t) = v sn (t) - v bp0 (t). v on(rms) = 0.638v lcd . v state2 (t) = v sn (t) - v bp1 (t). v off(rms) = 0.333v lcd . fig 8. waveforms for the 1:3 multiplex drive mode with 1 3 bias mgl748 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 (a) waveforms at driver. bp2 s n s n+1 s n+2 t fr v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 0 v v lcd 2v lcd / 3 - 2v lcd / 3 v lcd / 3 - v lcd / 3 - v lcd 0 v v lcd 2v lcd / 3 - 2v lcd / 3 v lcd / 3 - v lcd / 3 - v lcd v ss v lcd 2v lcd / 3 v lcd / 3
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 12 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 7.4.4 1:4 multiplex drive mode when four backplanes are provided in the lcd, the 1:4 multiplex drive mode applies, as shown in figure 9 . v state1 (t) = v sn (t) - v bp0 (t). v on(rms) = 0.577v lcd . v state2 (t) = v sn (t) - v bp1 (t). v off(rms) = 0.333v lcd . fig 9. waveforms for the 1:4 multiplex drive mode with 1 3 bias mgl749 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 bp2 (a) waveforms at driver. bp3 sn sn+1 sn+2 sn+3 t fr v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 0 v v lcd 2v lcd / 3 - 2v lcd / 3 v lcd / 3 - v lcd / 3 - v lcd 0 v v lcd 2v lcd / 3 - 2v lcd / 3 v lcd / 3 - v lcd / 3 - v lcd v ss v lcd 2v lcd / 3 v lcd / 3
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 13 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 7.5 oscillator the internal logic and the lcd drive signals of the pcf8534a are timed by the frequency f clk , which equals either the built-in oscillator frequency f osc or the external clock frequency f clk(ext) . the clock frequency f clk determines the lcd frame frequency (f fr ). 7.5.1 internal clock the internal oscillator is enabled by connecting pin osc to pin v ss . in this case, the output from pin clk is the clock signal for any cascaded pcf8534a in the system. after power-on, sda must be high to guarantee that the clock starts. 7.5.2 external clock connecting pin osc to v dd enables an external clock source. pin clk becomes the external clock input. a clock signal must always be applied to the device, removing the clock can freeze the lcd in a dc state. 7.6 timing the timing of the pcf8534a sequences the internal data ?ow of the device. this includes the transfer of display data from the display ram to the display segment outputs. in cascaded applications, the synchronization signal ( sync) maintains the correct timing relationship between all the pcf8534as in the system. the timing also generates the lcd frame frequency which is derived as an integer division of the clock frequency (see t ab le 6 ). when an external clock is used, the frame frequency is a ?xed division of the internal clock or the frequency applied to pin clk. 7.7 display register the display register holds the display data while the corresponding multiplex signals are generated. there is a one-to-one relationship between the data in the display register, the lcd segment outputs and one column of the display ram. 7.8 segment outputs the lcd drive section includes 60 segment outputs (s0 to s59) which must be connected directly to the lcd. the segment output signals are generated based on the multiplexed backplane signals and with data resident in the display register. when less than 60 segment outputs are required the unused segment outputs must be left open-circuit. table 6. lcd frame frequencies frame frequency nominal frame frequency (hz) 64 f fr f clk 24 --------- =
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 14 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 7.9 backplane outputs the lcd drive section includes four backplane outputs: bp0 to bp3. the backplane output signals are generated based on the selected lcd drive mode. ? in 1:4 multiplex drive mode: bp0 to bp3 must be connected directly to the lcd. if less than four backplane outputs are required the unused outputs can be left as an open-circuit. ? in 1:3 multiplex drive mode: bp3 carries the same signal as bp1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. ? in 1:2 multiplex drive mode: bp0 and bp2, bp1 and bp3 respectively carry the same signals and can also be paired to increase the drive capabilities. ? in static drive mode: the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.10 display ram the display ram is static 60 4-bit ram which stores lcd data. logic 1 in the ram bit map indicates the on-state of the corresponding lcd segment, logic 0 indicates the off-state. there is a direct relationship between ram addresses and the segment outputs and the individual bits of a ram word and the backplane outputs. the ?rst ram row corresponds to the 60 segments operated with respect to backplane bp0 (see figure 10 ). in multiplexed lcd applications, the segment data of rows 1 to 4 of the display ram are time-multiplexed with bp0, bp1, bp2 and bp3, respectively. when display data is transmitted to the pcf8534a, the display bytes received are stored in the display ram based on the selected lcd drive mode. data is stored as it arrives and does not wait for the acknowledge cycle. depending on the current multiplexer mode data is stored singularly, in pairs, triplets or quadruplets. in 1:2 multiplexer mode for example, ram data is stored every second bit. an example of a 7-segment numeric display illustrating the storage order for all drive modes is shown in figure 11 . the ram storage organization applies equally to other lcd types. display ram bit map showing the direct relationship between backplane outputs, display ram addresses and segment outputs and between bits in a ram word and backplane outputs. fig 10. display ram bit map 0 0 1 2 3 1 2 3 4 55 56 57 58 59 display ram addresses (columns)/segment outputs (s) display ram bits (rows)/ backplane outputs (bp) 001aah617
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 15 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates the following applies to figure 11 : ? static drive mode: the eight transmitted data bits are placed in row 0 to eight successive display ram addresses. ? 1:2 multiplex drive mode: the eight transmitted data bits are placed in row 0 and 1 to four successive display ram addresses. ? 1:3 multiplex drive mode: the eight transmitted data bits are placed in row 0, 1 and 2 to three successive addresses. however, bit 2 of the third address is left unchanged. this last bit can, if necessary, be controlled by an additional transfer to this address but avoid overriding adjacent data because full bytes are always transmitted. ? 1:4 multiplex drive mode: the eight transmitted data bits are placed in row 0, 1, 2 and 3 to two successive display ram addresses. 7.11 data pointer the addressing mechanism for the display ram is realized using the data pointer. this allows the loading of an individual display data byte or a series of display data bytes, into any location of the display ram. the sequence commences with the initialization of the data pointer by the load data pointer command. after this, the data byte is stored starting at the display ram address indicated by the data pointer (see figure 11 ). once each byte is stored, the data pointer is automatically incremented based on the selected lcd con?guration. the contents of the data pointer are incremented as follows: ? in static drive mode by eight. ? in 1:2 multiplex drive mode by four. ? in 1:3 multiplex drive mode by three. ? in 1:4 multiplex drive mode by two. if an i 2 c-bus data access terminates early, the state of the data pointer is unknown. consequently, the data pointer must be rewritten prior to further ram accesses.
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pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 17 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 7.12 subaddress counter the storage of display data is conditioned by the contents of the subaddress counter. storage is allowed only when the contents of the subaddress counter agree with the hardware subaddress applied to a0, a1 and a2. the subaddress counter value is de?ned by the device select command (see t ab le 12 ). if the contents of the subaddress counter and the hardware subaddress do not agree then data storage is blocked but the data pointer will be incremented as if data storage had taken place. in cascaded applications each pcf8534a in the cascade must be addressed separately. initially, the ?rst pcf8534a is selected by sending the device select command matching the ?rst device's hardware subaddress. then the data pointer is set to the preferred display ram address by sending the load data pointer command. once the display ram of the ?rst pcf8534a has been written, the second pcf8534a is selected by sending the device select command again. this time however the command matches the second device's hardware subaddress. next the load data pointer command is sent to select the preferred display ram address of the second pcf8534a. this last step is very important because during writing data to the ?rst pcf8534a, the data pointer of the second pcf8534a is incremented. in addition, the hardware subaddress should not be changed whilst the device is being accessed on the i 2 c-bus interface. 7.13 output bank selector the output bank selector (see t ab le 13 ), selects one of the four bits per display ram address for transfer to the display register. the actual bit selected depends on the lcd drive mode in operation and on the instant in the multiplex sequence. ? in 1:4 multiplex mode: all ram addresses of bit 0 are selected, followed sequentially by the contents of bit 1, bit 2 and then bit 3. ? in 1:3 multiplex mode: bits 0, 1 and 2 are selected sequentially. ? in 1:2 multiplex mode: bits 0 and 1 are selected. ? in the static mode: bit 0 is selected. the sync signal resets these sequences to the following starting points: bit 3 for 1:4 multiplex, bit 2 for 1:3 multiplex, bit 1 for 1:2 multiplex and bit 0 for static mode. the pcf8534a includes a ram bank switching feature in the static and 1:2 multiplex drive modes. in static drive mode, the bank select command may request the contents of bit 2 to be selected for display instead of the contents of bit 0. in 1:2 multiplex drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. this enables preparation of display information in an alternative bank and the ability to switch to it once it has been assembled. 7.14 input bank selector the input bank selector loads display data into the display ram based on the selected lcd drive con?guration. using the bank select command, display data can be loaded in bit 2 into static drive mode or in bits 2 and 3 into 1:2 multiplex drive mode. the input bank selector functions independently to the output bank selector.
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 18 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 7.15 blinker the display blinking capabilities of the pcf8534a are very versatile. the whole display can be blinked at frequencies set by the blink select command (see t ab le 14 ). the blinking frequencies are fractions of the clock frequency. the ratios between the clock and blinking frequencies depend on the mode in which the device is operating (see t ab le 7 ). an additional feature is for the arbitrary selection of lcd segments to be blinked. this applies to the static and 1:2 multiplex drive modes and is implemented without any communication overheads. using the output bank selector, the displayed ram banks are exchanged with alternate ram banks at the blinking frequency. this mode can also be speci?ed by the blink select command. in the 1:3 and 1:4 multiplex modes, where no alternate ram bank is available, groups of lcd segments can be blinked by selectively changing the display ram data at ?xed time intervals. if the entire display needs to be blinked at a frequency other than the nominal blinking frequency, this can be done using the mode set command to set and reset the display enable bit e at the required rate (see t ab le 10 ). 8. basic architecture 8.1 characteristics of the i 2 c-bus the i 2 c-bus provides bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). when connected to the output stages of a device, both lines must be connected to a positive supply via a pull-up resistor. data transfer is initiated only when the bus is not busy. 8.1.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse. changes in the data line at this time will be interpreted as a control signal. bit transfer is illustrated in figure 12 . table 7. blink frequencies assuming that f clk = 1536 hz. blink mode operating mode ratio blink frequency off - blinking off 1 2 hz 2 1 hz 3 0.5 hz f blink f clk 768 --------- = f blink f clk 1536 ----------- - = f blink f clk 3072 ----------- - =
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 19 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 8.1.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low change of the data line, while the clock is high, is de?ned as the start condition (s). a low-to-high change of the data line, while the clock is high, is de?ned as the stop condition (p). the start and stop conditions are illustrated in figure 13 . 8.1.2 system con?guration a device generating a message is a transmitter and a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. the system con?guration is illustrated in figure 14 . 8.1.3 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. fig 12. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 13. de?nition of start and stop conditions mbc622 sda scl p stop condition sda scl s start condition fig 14. system con?guration mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 20 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates ? a slave receiver which is addressed must generate an acknowledge after the reception of each byte. ? a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). ? a master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the master receiver must leave the data line high during the 9th pulse to not acknowledge. the master will now generate a stop condition. acknowledgement on the i 2 c-bus is illustrated in figure 15 . 8.1.4 pcf8534a i 2 c-bus controller the pcf8534a acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers or transmit data to an i 2 c-bus master receiver. the only data output from the pcf8534a are the acknowledge signals of the selected devices. device selection depends on the i 2 c-bus slave address, the transferred command data and the hardware subaddress. in single device application, the hardware subaddress inputs a0, a1 and a2 are normally tied to v ss which de?nes the hardware subaddress 0. in multiple device applications a0, a1 and a2 are tied to v ss or v dd using a binary coding scheme so that no two devices with a common i 2 c-bus slave address have the same hardware subaddress. 8.1.5 input ?lters to enhance noise immunity in electrically adverse environments, rc low-pass ?lters are provided on the sda and scl lines. fig 15. acknowledgement of the i 2 c-bus mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 21 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 8.2 i 2 c-bus protocol two i 2 c-bus slave addresses (0111 000 and 0111 001) are reserved for the pcf8534a. the least signi?cant bit of the slave address is bit r/ w. the pcf8534a is a write-only device. it will not respond to a read access, so this bit should always be logic 0. the second bit of the slave address is de?ned by the level tied at input sa0. two displays controlled by pcf8534a can be recognized on the same i 2 c-bus which allows: ? up to 16 pcf8534as on the same i 2 c-bus for very large lcd applications ? the use of two types of lcd multiplex on the same i 2 c-bus the i 2 c-bus protocol is shown in figure 17 . the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of the available pcf8534a slave addresses. all pcf8534as with the same sa0 level acknowledge in parallel to the slave address. all pcf8534as with the alternative sa0 level ignore the whole i 2 c-bus transfer. after acknowledgement, the control byte is sent de?ning if the next byte is ram or command information. the control byte also de?nes if the next byte is a control byte or further ram/command data (see figure 16 and t ab le 8 ). in this way it is possible to con?gure the device and then ?ll the display ram with little overhead. the command bytes and control bytes are also acknowledged by all addressed pcf8534as connected to the bus. the display bytes are stored in the display ram at the address speci?ed by the data pointer and the subaddress counter. both data pointer and subaddress counter are automatically updated. the acknowledgement after each byte is made only by the (a0, a1 and a2) addressed pcf8534a. after the last display byte, the i 2 c-bus master issues a stop condition (p). alternatively a start may be issued to restart i 2 c-bus access. fig 16. control byte format table 8. load data pointer command bit description bit symbol value description 7co continue bit 0 last control byte 1 control bytes continue 6rs register selection 0 command register 1 data register 5 to 0 - not relevant mgl753 not relevant co 76 543210 rs msb lsb
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 22 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 8.3 command decoder the command decoder identi?es command bytes that arrive on the i 2 c-bus. there are ?ve commands: fig 17. i 2 c-bus protocol examples a) transmit two bytes of ram data mgl752 s a 0 s 01110 0 0 control byte slave address ram/command byte ram data m s b l s b a a p r/w = 0 s a 0 s 01110 0 01 0 a a a p ram data a b) transmit two command bytes command s a 0 s 01110 0 10 0 a a a p command a a c) transmit one command byte and two ram date bytes command s a 0 s 01110 0 10 00 01 0 a a a p ram data a ram data a a c o r s table 9. de?nition of commands command opcode reference mode set 1 100ebm1m0 t ab le 10 load data pointer 0 p6 p5 p4 p3 p2 p1 p0 t ab le 11 device select 1 1100a2a1a0 t ab le 12 bank select 1 11110i o t ab le 13 blink select 1 1110abf1bf0 t ab le 14 table 10. mode set command bit description bit symbol value description 7 to 4 - 1100 ?xed value 3e display status the possibility to disable the display allows implementation of blinking under external control 0 disabled (blank) 1 enable 2b lcd bias con?guration 0 1 3 bias 1 1 2 bias
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 23 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates [1] the bank select command has no effect in 1:3 or 1:4 multiplex drive modes. 1 to 0 m[1:0] lcd drive mode selection 01 static; 1 backplane 10 1:2 multiplex; 2 backplanes 11 1:3 multiplex; 3 backplanes 00 1:4 multiplex; 4 backplanes table 11. load data pointer command bit description see section 7.11 . bit symbol value description 7 - 0 ?xed value 6 to 0 p[6:0] 000 0000 to 011 1011 7-bit binary value of 0 to 59 table 12. device select command bit description see section 7.12 . bit symbol value description 7 to 3 - 1 1100 ?xed value 2 to 0 a[2:0] 000 to 111 3-bit binary value of 0 to 7 table 13. bank select command bit description see section 7.10 , section 7.11 , section 7.12 , section 7.13 and section 7.14 . bit symbol value description static 1:2 multiplex [1] 7 to 2 - 11 1110 ?xed value 1i input bank selection : storage of arriving display data 0 ram bit 0 ram bits 0 and 1 1 ram bit 2 ram bits 2 and 3 0o output bank selection : retrieval of lcd display data 0 ram bit 0 ram bits 0 and 1 1 ram bit 2 ram bits 2 and 3 table 10. mode set command bit description continued bit symbol value description
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 24 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates [1] only normal blinking can be selected in multiplexer 1:3 or 1:4 drive modes. 8.4 display controller the display controller executes the commands identi?ed by the command decoder. it contains the status registers of the pcf8534a and coordinates their effects. the controller also loads display data into the display ram as required by the storage order. table 14. blink select command bit description see section 7.15 . bit symbol value description 7 to 3 - 1 1110 ?xed value 2a blink mode selection 0 normal blinking [1] 1 blinking by alternating display ram banks 1 to 0 bf[1:0] blink frequency selection 00 off 01 1 10 2 11 3
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 25 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 9. internal circuitry fig 18. device protection diagram sa0 v dd v dd v ss v ss v lcd v ss sda 001aah615 v ss scl v ss clk v dd v ss osc v dd v ss sync v dd v ss a0, a1, a2 v dd v ss bp0, bp1, bp2, bp3 v lcd v ss s0 to s59 v lcd v ss
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 26 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 10. limiting values [1] pins sda, scl, clk, sync, sa0, osc and a0 to a2. [2] pins s0 to s59 and bp0 to bp3. [3] hbm: human body model, according to jesd22-a114. [4] mm: machine model, according to jesd22-a115. [5] cdm: charged device model, according to jesd22-c101. [6] latch-up testing, according to jesd78. caution static voltages across the liquid crystal display can build up when the lcd supply voltage (v lcd ) is on while the ic supply voltage (v dd ) is off, or vice versa. this may cause unwanted display artifacts. to avoid such artifacts, v lcd and v dd must be applied or removed together. table 15. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.5 +6.5 v i dd supply current - 50 +50 ma v lcd lcd supply voltage - 0.5 +7.5 v i dd(lcd) lcd supply current - 50 +50 ma i ss ground supply current - 50 +50 ma v i input voltage [1] - 0.5 +6.5 v i i input current [1] - 10 +10 ma v o output voltage [1] - 0.5 +6.5 v [2] - 0.5 +7.5 v i o output current [1] [2] - 10 +10 ma p tot total power dissipation - 400 mw p/out power dissipation per output - 100 mw t stg storage temperature - 65 +150 c v esd electrostatic discharge voltage hbm [3] - 2000 v mm [4] - 200 v cdm [5] - 2000 v i lu latch-up current [6] - 100 ma
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 27 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 11. static characteristics [1] lcd outputs are open circuit; inputs at v ss or v dd ; external clock with 50 % duty factor; i 2 c-bus inactive. [2] not tested, design speci?cation only. [3] c bpl = backplane capacitance. [4] outputs measured individually and sequentially. [5] c sgm = segment capacitance. table 16. static characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 6.5 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies v dd supply voltage 1.8 - 5.5 v v lcd lcd supply voltage 2.5 - 6.5 v i dd supply current f clk = 1536 hz [1] -820 m a i dd(lcd) lcd supply current f clk = 1536 hz [1] -2460 m a logic v i input voltage v ss - 0.5 v dd + 0.5 v v il low-level input voltage on pins clk, sync, osc, a0 to a2 and sa0 v ss - 0.3v dd v v ih high-level input voltage on pins clk, sync, osc, a0 to a2 and sa0 0.7v dd -v dd v v por power-on reset voltage 1.0 1.3 1.6 v i ol low-level output current v ol = 0.4 v; v dd = 5 v; on pins clk and sync 1--ma i oh high-level output current v oh = 4.6 v; v dd = 5 v; on pin clk - 1-- ma i l leakage current v i = v dd or v ss ; on pins sa0, a0 to a2 and clk - 1-+1 m a v i = v dd ; on pin osc - 1-+1 m a c i input capacitance [2] --7pf i 2 c-bus; pins sda and scl v i input voltage v ss - 0.5 - 5.5 v v il low-level input voltage pin scl v ss - 0.3v dd v pin sda v ss - 0.2v dd v v ih high-level input voltage 0.7v dd - 5.5 v i ol low-level output current v ol = 0.4 v; v dd = 5 v; on pin sda 3 - - ma i l leakage current v i = v dd or v ss - 1-+1 m a c i input capacitance [2] --7pf lcd outputs output pins bp0, bp1, bp2 and bp3 v bp voltage on pin bp c bpl = 35 nf [3] - 100 - +100 mv r bp resistance on pin bp v lcd = 5 v [4] - 1.5 10 k w output pins s0 to s59 v s voltage on pin s c sgm = 35 nf [5] - 100 - +100 mv r s resistance on pin s v lcd = 5 v [4] - 6.0 13.5 k w
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 28 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 12. dynamic characteristics [1] typical output (duty cycle d = 50 %). [2] all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . table 17. dynamic characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 6.5 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit clock internal: output pin clk f osc oscillator frequency v dd = 5 v [1] 960 1536 3046 hz external: input pin clk f clk(ext) external clock frequency v dd = 5 v 797 1536 3046 hz t clk(h) high-level clock time 130 - - m s t clk(l) low-level clock time 130 - - m s synchronization: input pin sync t pd(sync_n) sync propagation delay - 30 - ns t sync_nl sync low time 1 - - m s outputs: pins bp0 to bp3 and s0 to s59 t pd(drv) driver propagation delay v lcd = 5 v - - 30 m s i 2 c-bus: timing [2] pin scl f scl scl frequency - - 400 khz t low low period of the scl clock 1.3 - - m s t high high period of the scl clock 0.6 - - m s pin sda t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns pins scl and sda t buf bus free time between a stop and start condition 1.3 - - m s t su;sto set-up time for stop condition 0.6 - - m s t hd;sta hold time (repeated) start condition 0.6 - - m s t su;sta set-up time for a repeated start condition 0.6 - - m s t r rise time of both sda and scl signals - - 0.3 m s t f fall time of both sda and scl signals - - 0.3 m s c b capacitive load for each bus line - - 400 pf t w(spike) spike pulse width - - 50 ns
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 29 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates fig 19. driver timing waveforms fig 20. i 2 c-bus timing waveforms 001aah618 0.7v dd 0.3v dd 0.7v dd 0.3v dd 1 / f clk t pd(sync_n) t pd(sync_n) t clk(h) t clk(l) sync clk 0.5 v 0.5 v t pd(drv) bp0 to bp3, and s0 to s59 t sync_nl (v dd = 5 v) sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 30 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 13. application information 13.1 cascaded operation large display con?gurations of up to 16 pcf8534as can be recognized on the same i 2 c-bus by using the 3-bit hardware subaddress (a0, a1 and a2) and the programmable i 2 c-bus slave address (sa0). if cascaded pcf8534as are synchronized, they can share the backplane signals from one of the devices in the cascade. this is cost-effective in large lcd applications because the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. the other pcf8534as in the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see figure 21 ). table 18. addressing cascaded pcf8534a cluster bit sa0 pin a2 pin a1 pin a0 device 100000 0011 0102 0113 1004 1015 1106 1117 210008 0019 01010 01111 10012 10113 11014 11115
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 31 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates the sync line is provided to maintain the correct synchronization between all cascaded pcf8534as. synchronization is guaranteed after a power-on reset. the only time that sync is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments or by de?ning a multiplex mode when pcf8534as with different sa0 levels are cascaded). sync is organized as an input/output pin. the output selection is realized as an open-drain driver with an internal pull-up resistor. a pcf8534a asserts the sync line at the onset of its last active backplane signal and monitors the sync line at all other times. if synchronization in the cascade is lost, it is restored by the ?rst pcf8534a to assert sync. the timing relationship between the backplane waveforms and the sync signal for the various drive modes of the pcf8534a are shown in figure 22 . fig 21. cascaded pcf8534a con?guration host micro- processor/ micro- controller sda scl clk osc sync 60 segment drives 4 backplanes 60 segment drives lcd panel pcf8534a a0 a1 a2 sa0 v ss v ss v ss v dd v dd v lcd v lcd v dd v lcd 001aah619 sda scl sync clk osc bp0 to bp3 (open-circuit) a0 a1 a2 sa0 pcf8534a bp0 to bp3 r t r 2c b
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 32 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates the contact resistance between the sync pins of cascaded devices must be controlled. if the resistance is too high, the device will not be able to synchronize properly. t ab le 19 shows the maximum contact resistance values. fig 22. synchronization of the cascade for various pcf8534a drive modes table 19. sync contact resistance number of devices maximum contact resistance 2 6000 w 3 to 5 2200 w 6 to 10 1200 w 11 to 16 700 w t fr = f fr 1 bp0 sync bp0 (1/2 bias) sync bp0 (1/3 bias) (a) static drive mode. (b) 1:2 multiplex drive mode. (c) 1:3 multiplex drive mode. (d) 1:4 multiplex drive mode. bp0 (1/3 bias) sync sync bp0 (1/3 bias) mgl755
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 33 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 14. package outline fig 23. package outline sot315-1 (lqfp80) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 0.5 14.15 13.85 1.45 1.05 7 0 o o 0.15 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.30 sot315-1 136e15 ms-026 00-01-19 03-02-25 d (1) (1) (1) 12.1 11.9 h d 14.15 13.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 20 c d h b p e h a 2 v m b d z d a z e e v m a x 1 80 61 60 41 40 21 y pin 1 index w m w m 0 5 10 mm scale lqfp80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315-1
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 34 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 15. bare die outline fig 24. pcf8534au die outline references outline version european projection issue date iec jedec jeita pcf8534au pcf8534au notes 1. pad size 2. passivation opening 3. marking code unit mm max nom min 0.38 0.08 2.91 0.06 0.05 0.10 a dimensions (mm are the original dimensions) wire bond die; 76 bonding pads; 2.91 x 2.62 x 0.38 mm 0 0.5 scale 1 mm d e 2.62 e p 1 (1) p 2 (2) p 3 (1) p 4 (2) 0.09 f a detail x p 2 p 1 p 3 p 4 e d e e x y 0 x 0 c1 c2 08-08-06 pc8534a-1 (3) 24 43 64 76 1 3 4 63 44 23
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 35 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates table 20. bonding pad locations symbol pad coordinates [1] description x ( m m) y ( m m) sda 1 - 1384.4 - 280 i 2 c-bus serial data input and output scl 2 - 1384.4 - 760.5 i 2 c-bus serial clock input clk 3 - 1384.4 - 945 external clock input and output v dd 4 - 978.7 - 1238 supply voltage sync 5 - 829.3 - 1238 cascade synchronization input and output osc 6 - 714.3 - 1238 enable input for internal oscillator a0 7 - 584.3 - 1238 subaddress counter input a1 8 - 454.3 - 1238 a2 9 - 324.3 - 1238 sa0 10 - 194.3 - 1238 i 2 c-bus slave address input 0 v ss 11 - 64.3 - 1238 ground v lcd 12 68.7 - 1238 input of lcd supply voltage s0 13 173.7 - 1238 lcd segment output s1 14 253.7 - 1238 s2 15 333.7 - 1238 s3 16 413.7 - 1238 s4 17 493.7 - 1238 s5 18 573.7 - 1238 s6 19 653.7 - 1238 s7 20 733.7 - 1238 s8 21 813.7 - 1238 s9 22 893.7 - 1238 s10 23 973.7 - 1238 s11 24 1384.4 - 841 s12 25 1384.4 - 761 s13 26 1384.4 - 681 s14 27 1384.4 - 601 s15 28 1384.4 - 521 s16 29 1384.4 - 441 s17 30 1384.4 - 361 s18 31 1384.4 - 281 s19 32 1384.4 - 201 s20 33 1384.4 - 121 s21 34 1384.4 - 41 s22 35 1384.4 39 s23 36 1384.4 119 s24 37 1384.4 301.6 s25 38 1384.4 381.6 s26 39 1384.4 461.6 s27 40 1384.4 541.6
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 36 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates [1] all coordinates are referenced in m m to the center of the die (see figure 24 ). s28 41 1384.4 621.6 lcd segment output s29 42 1384.4 701.6 s30 43 1384.4 781.6 s31 44 896.5 1239.4 s32 45 816.5 1239.4 s33 46 736.5 1239.4 s34 47 576.5 1239.4 s35 48 496.5 1239.4 s36 49 416.5 1239.4 s37 50 336.5 1239.4 s38 51 256.5 1239.4 s39 52 176.5 1239.4 s40 53 96.5 1239.4 s41 54 16.5 1239.4 s42 55 - 63.5 1239.4 s43 56 - 143.5 1239.4 s44 57 - 223.5 1239.4 s45 58 - 303.5 1239.4 s46 59 - 463.5 1239.4 s47 60 - 543.5 1239.4 s48 61 - 623.5 1239.4 s49 62 - 703.5 1239.4 s50 63 - 783.5 1239.4 s51 64 - 1384.4 935 s52 65 - 1384.4 855 s53 66 - 1384.4 775 s54 67 - 1384.4 695 s55 68 - 1384.4 615 s56 69 - 1384.4 535 s57 70 - 1384.4 375 s58 71 - 1384.4 295 s59 72 - 1384.4 215 bp0 73 - 1384.4 125 lcd backplane output bp1 74 - 1384.4 45 bp2 75 - 1384.4 - 35 bp3 76 - 1384.4 - 115 table 20. bonding pad locations continued symbol pad coordinates [1] description x ( m m) y ( m m)
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 37 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates [1] all coordinates are referenced in m m to the center of the die (see figure 24 ). 16. handling information inputs and outputs are protected against electrostatic discharge in normal handling. however, to be completely safe you must take normal precautions appropriate to handling mos devices; see jesd625-a and/or iec61340-5 . fig 25. alignment marks table 21. alignment mark locations [1] symbol x ( m m) y ( m m) c1 - 1387 1190 c2 1335 1242 f - 1345 - 1173 001aai649 ref ref ref c2 c1 f
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 38 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 17. packing information fig 26. tray details for pcf8534au/da/1 fig 27. tray alignment for pcf8534au/da/1 001aai625 e f b d c a x.1 x y 1.2 1.3 2.2 3.1 1.y 2.1 1.1 001aai650 pc8534a-1
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 39 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 18. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 18.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages table 22. tray dimensions symbol description value a pocket pitch in x direction 5.5 mm b pocket pitch in y direction 4.9 mm c pocket width in x direction 3.08 mm d pocket width in y direction 2.79 mm e tray width in x direction 50.8 mm f tray width in y direction 50.8 mm n number of pockets, x direction 8 m number of pockets, y direction 9
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 40 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 18.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities 18.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 28 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 23 and 24 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 28 . table 23. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 24. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 41 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 19. abbreviations msl: moisture sensitivity level fig 28. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 25. abbreviations acronym description cdm charged device model cmos complementary metal-oxide semiconductor esd electrostatic discharge hbm human body model ic integrated circuit lcd liquid crystal display mm machine model ram random access memory
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 42 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 20. revision history table 26. revision history document id release date data sheet status change notice supersedes pcf8534a_3 20081110 product data sheet - pcf8534a_2 modi?cations: ? added bare die product and document sections pcf8534a_2 20080604 product data sheet - pcf8534a_1 modi?cations: ? changes in section 7.10 on page 14 and section 7.12 on page 17 . ? added caution to section 10 on page 26 . ? changed figure 22 on page 32 . pcf8534a_1 20080423 product data sheet - -
pcf8534a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 10 november 2008 43 of 44 nxp semiconductors pcf8534a universal lcd driver for low multiplex rates 21. legal information 21.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 21.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 21.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. bare die all die are tested on compliance with their related technical speci?cations as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the nxp semiconductors storage and transportation conditions. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post-packing tests performed on individual die or wafers. nxp semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, nxp semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. all die sales are conditioned upon and subject to the customer entering into a written die sale agreement with nxp semiconductors through its legal department. 21.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 22. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors pcf8534a universal lcd driver for low multiplex rates ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 10 november 2008 document identifier: pcf8534a_3 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 23. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 lcd bias generator. . . . . . . . . . . . . . . . . . . . . . 6 7.3 lcd voltage selector . . . . . . . . . . . . . . . . . . . . 6 7.4 lcd drive mode waveforms . . . . . . . . . . . . . . . 8 7.4.1 static drive mode . . . . . . . . . . . . . . . . . . . . . . . 8 7.4.2 1:2 multiplex drive mode . . . . . . . . . . . . . . . . . . 9 7.4.3 1:3 multiplex drive mode . . . . . . . . . . . . . . . . . 11 7.4.4 1:4 multiplex drive mode . . . . . . . . . . . . . . . . . 12 7.5 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.5.1 internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.5.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.6 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.7 display register . . . . . . . . . . . . . . . . . . . . . . . . 13 7.8 segment outputs. . . . . . . . . . . . . . . . . . . . . . . 13 7.9 backplane outputs . . . . . . . . . . . . . . . . . . . . . 14 7.10 display ram . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.11 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.12 subaddress counter . . . . . . . . . . . . . . . . . . . . 17 7.13 output bank selector. . . . . . . . . . . . . . . . . . . . 17 7.14 input bank selector . . . . . . . . . . . . . . . . . . . . . 17 7.15 blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 basic architecture . . . . . . . . . . . . . . . . . . . . . . 18 8.1 characteristics of the i 2 c-bus . . . . . . . . . . . . . 18 8.1.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1.1.1 start and stop conditions . . . . . . . . . . . . . 19 8.1.2 system con?guration . . . . . . . . . . . . . . . . . . . 19 8.1.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.1.4 pcf8534a i 2 c-bus controller . . . . . . . . . . . . . 20 8.1.5 input ?lters . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.2 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21 8.3 command decoder . . . . . . . . . . . . . . . . . . . . . 22 8.4 display controller . . . . . . . . . . . . . . . . . . . . . . 24 9 internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 25 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26 11 static characteristics. . . . . . . . . . . . . . . . . . . . 27 12 dynamic characteristics . . . . . . . . . . . . . . . . . 28 13 application information. . . . . . . . . . . . . . . . . . 30 13.1 cascaded operation . . . . . . . . . . . . . . . . . . . . 30 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 33 15 bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 34 16 handling information . . . . . . . . . . . . . . . . . . . 37 17 packing information . . . . . . . . . . . . . . . . . . . . 38 18 soldering of smd packages . . . . . . . . . . . . . . 39 18.1 introduction to soldering. . . . . . . . . . . . . . . . . 39 18.2 wave and re?ow soldering . . . . . . . . . . . . . . . 39 18.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 40 18.4 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 40 19 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41 20 revision history . . . . . . . . . . . . . . . . . . . . . . . 42 21 legal information . . . . . . . . . . . . . . . . . . . . . . 43 21.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 43 21.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 21.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 43 21.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 43 22 contact information . . . . . . . . . . . . . . . . . . . . 43 23 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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